A CMOS Dynamic Comparator for Pipelined ADCs with Improved Speed/Power Ratio

作     者：刘珂 杨海钢 Liu Ke;Yang Haigang

作者机构：中国科学院电子学研究所传感技术国家重点实验室 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2008年第29卷第1期

页      码：75-81页

摘      要：This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution. Because the architecture is based on the coupled current sources and differential input pairs, this comparator＇s threshold voltage can be adjusted to a desired level. Compared with traditional comparators, this one shows significant improvement in area,power,and speed. Fabricated in 0.35μm CMOS technology,it occupies only 30μm × 70μm. Simulation and measurement results indicate the comparator has a sampling frequency up to 1GHz with 2Vpp differential input signal range and only 181μW power consumption under a 3.3V supply. The speed/power ratio reaches up to 5524GS/J.

主 题 词：CMOS comparator ADC 

学科分类：080903[080903] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.3321/j.issn:0253-4177.2008.01.014

馆 藏 号：203115520...