Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

作     者：Zhengzhou CAO Guozhu LIU Yanfei ZHANG Yueer SHAN Yuting XU Zhengzhou CAO;Guozhu LIU;Yanfei ZHANG;Yueer SHAN;Yuting XU

作者机构：No.58 Research InstituteChina Electronics Technology Group CorporationWuxi 214035China 

基　　金：supported by the National Natural Science Foundation of China(No.62174150) the Natural Science Foundation of Jiangsu Province,China(Nos.BK20211040 and BK20211041) 

出 版 物：《Frontiers of Information Technology & Electronic Engineering》 (信息与电子工程前沿（英文版）)

年 卷 期：2024年第25卷第4期

页      码：485-499页

摘      要：This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH *** programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be *** PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to *** intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization *** measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 *** programmable function of PLE works *** delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.

主 题 词：Field programmable gate array(FPGA) Programmable logic element(PLE) Boolean logic operation Look-up table Sense-Switch pFLASH Threshold voltage 

学科分类：080903[080903] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.1631/FITEE.2300454

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