DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

作     者：Wang Pengjun Yu Junjun 

作者机构：Institute of Circuits and Systems Ningbo University Ningbo 315211 China 

基　　金：Supported by the National Natural Science Foundation of China (No. 60273093) the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38) 

出 版 物：《Journal of Electronics(China)》 (电子科学学刊（英文版）)

年 卷 期：2007年第24卷第2期

页      码：225-231页

摘      要：First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

主 题 词：Circuit design Two-phase sinusoidal power clock Clock generator Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit 

学科分类：080902[080902] 0809[工学-计算机类] 08[工学] 

D　O　I：10.1007/s11767-005-0170-2

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