Design and optimization of an ultra-wide frequency range CMOS divide-by-two circuit

作     者：陆波 梅年松 陈虎 洪志良 

作者机构：State Key Laboratory of ASIC and SystemFudan University 

基　　金：Project supported by the National High Technology Research and Development Program of China(No.SQ2008AA01Z4473469) 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2010年第31卷第11期

页      码：122-126页

摘      要：A novel toggled flip-flop（TFF） divide-by-two circuit（DTC） and its optimization method based on a large-signal analysis approach are *** reducing the output RC constant in tracking mode and making it large in latching mode,compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly *** in a SMIC 0.13μm RF CMOS process with a 1.2 V power supply,it can work under an ultra-wide frequency band ranging from 320 MHz to 29.6 *** results show that two phase-locked loops（PLLs） with the proposed DTC can achieve in-band phase noise of-94 dBc/Hz @ 10 kHz under 4224 MHz operating frequency and-84 dBc/Hz @ 10 kHz under 10 GHz operating frequency,respectively. The power consumption of the proposed DTC is reduced by almost 50%compared with the conventional counterparts.

主 题 词：TFF DTC PLL ultra-wide frequency range optimization method in-band phase noise 

学科分类：080902[080902] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.1088/1674-4926/31/11/115011

馆 藏 号：203141008...