A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

作     者：张利 池保勇 姚金科 王志华 陈弘毅 

作者机构：清华大学微电子学研究所北京100084 清华大学电子工程系北京100084 

基　　金：国家重点基础研究发展计划(批准号:G2000036508) 国家自然科学基金(批准号:90407006,60475018)资助项目~~ 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2006年第27卷第12期

页      码：2106-2111页

摘      要：A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the *** transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.

主 题 词：CMOS fractional-N Gaussian minimum shift keying phase-locked loop~ sigma-delta 

学科分类：080902[080902] 0809[工学-计算机类] 08[工学] 

核心收录：

馆 藏 号：203142799...