An Improved High Fan-in Domino Circuit for High Performance Microprocessors

作     者：冯超超 陈迅 衣晓飞 张民选 Feng Chaochao;Chen Xun;Yi Xiaofei;Zhang Minxuan

作者机构：国防科技大学计算机学院并行与分布处理国防重点实验室长沙410073 

基　　金：the National High-Tech Research and Development Program of China(No.2005AA110020) 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2008年第29卷第9期

页      码：1740-1744页

摘      要：An improved high fan-in domino circuit is proposed. The nMOS pull-down network of the circuit is divided into several blocks to reduce the capacitance of the dynamic node and each block only needs a small keeper transistor to maintain the noise margin. Because we omit the footer transistor, the circuit has better performance than the standard domino circuit. A 64-input OR-gate implemented with the structure is simulated using HSPICE under typical conditions of 0.13μm CMOS technology. The average delay of the circuit is 63.9ps, the average power dissipation is 32.4μW, and the area is l15μm^2. Compared to compound domino logic, the proposed circuit can reduce delay and power dissipation by 55% and 38%, respectively.

主 题 词：high fan-in domino logic high performance keeper transistor 

学科分类：08[工学] 081201[081201] 0812[工学-测绘类] 

核心收录：

D　O　I：10.3321/j.issn:0253-4177.2008.09.019

馆 藏 号：203147983...