The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

作     者：陈启星 罗启宇 

作者机构：Hunan Urban Construction College China National Electronics Import&Export Corp. 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2013年第34卷第3期

页      码：121-126页

摘      要：At present,the architecture of a digital-to-analog converter(DAC) in essence is based on the weight current,and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase,which is 2^(n-1) times of its least weight *** for a dual weight resistance chain type DAC,by using the weight voltage manner to D/A conversion,the D/A signal current is fixed to chain current I_(cha);it is only 1/2^(n-1) order of magnitude of the average signal current value of the weight current type *** principle is:n pairs dual weight resistances form a resistance chain,which ensures the constancy of the chain current;if digital signals control the total weight resistance from the output point to the zero potential point,that could directly control the total weight voltage of the output point,so that the digital signals directly turn into a sum of the weight voltage signals;thus the following goals are realized:(1) the total current is less than 200μA;(2) the total power consumption is less than 2 m W;(3) an 18-bit conversion can be realized by adopting a multi-grade structure;(4) the chip area is one order of magnitude smaller than the subsection current-steering type DAC;(5) the error depends only on the error of the unit resistance,so it is smaller than the error of the subsection current-steering type DAC; (6) the conversion time is only one action time of switch on or off,so its speed is not lower than the present DAC.

主 题 词：DAC weight resistance dual resistance resistance chain weight voltage weight current 

学科分类：080902[080902] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.1088/1674-4926/34/3/035010

馆 藏 号：203150073...