A front-end automation tool supporting design, verification and reuse of SOC

作     者：严晓浪 余龙理 王界兵 

作者机构：InstituteofVLSIDesignZhejiangUniversityHangzhou310027China C-SkyMicrosvstemsHangzhou310032China 

出 版 物：《Journal of Zhejiang University Science》 (浙江大学学报（自然科学英文版）)

年 卷 期：2004年第5卷第9期

页      码：1102-1105页

摘      要：This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

主 题 词：System-On-Chip Verilog HDL Verification Reuse 

学科分类：080903[080903] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.1631/jzus.2004.1102

馆 藏 号：203162084...