SIMULATION AND PERFORMANCE ANALYSIS OF NETWORK ON CHIP ARCHITECTURES

作     者：葛芬 吴宁 Ge Fen;Wu Ning

作者机构：南京航空航天大学信息科学与技术学院 

基　　金：Supported by the Natural Science Foundation of China(61076019) the China Postdoctoral Science Foundation(20100481134) the Natural Science Foundation of Jiangsu Province(BK2008387) the Graduate Student Innovation Foundation of Jiangsu Province(CX07B-105z) 

出 版 物：《Transactions of Nanjing University of Aeronautics and Astronautics》 (南京航空航天大学学报（英文版）)

年 卷 期：2010年第27卷第4期

页      码：326-332页

摘      要：The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）*** further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic *** results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given ***,a MPEG4 decoder is mapped on different NoC *** prove the effectiveness of the evaluation method.

主 题 词：microprocessor chips architecture network on chip system on chip performance analysis 

学科分类：080903[080903] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.3969/j.issn.1005-1120.2010.04.007

馆 藏 号：203179938...