Power-optimal encoding for low-power address bus

作     者：孙海珺 邵志标 

作者机构：School of Electronics and Information Engineering Xi’an Jiaotong University 

基　　金：Sponsored by the National High Technology Research and Development Prgram of China(Grant No.2005AA1Z1100) 

出 版 物：《Journal of Harbin Institute of Technology(New Series)》 (哈尔滨工业大学学报（英文版）)

年 卷 期：2007年第14卷第5期

页      码：652-656页

摘      要：This paper presented a novel bus encoding method to reduce the switching activity on address buses and hence reduce power dissipation. Dynamic-sorting encoding(DSE) method reduces the power dissipation of address bus based on the dynamic reordering of the modified offset address bus lines. This method reorders the ten least significant bits of offset address according to the range of offset address, and the optimal sorting pattern is transmitted through the high bits of address bus without the need for redundant bus lines. The experimental results by using an instruction set simulator and SPEC2000 benchmarks show that DSE method can reduce signal transitions on the address bus by 88.2%, and the actual overhead of the encoder circuit is estimated after encoder is designed and synthesized in 0.18-μm CMOS technology. The results show that DSE method outperforms the low-power encoding schemes presented in the past.

主 题 词：bus encoding switching activity address bus low-power CMOS 

学科分类：0810[工学-土木类] 08[工学] 0805[工学-能源动力学] 081201[081201] 0812[工学-测绘类] 

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