Chip-level space-time equalization receiver scheme for MIMO HSDPA systems

作     者：周志刚 程时昕 陈明 Zhou Zhigang;Cheng Shixin;Chen Ming

作者机构：东南大学移动通信国家重点实验室南京210096 

基　　金：TheNationalHighTechnologyResearchandDevelopmentProgramofChina ( 863Program ) (No .2 0 0 2AA12 3 0 3 1)  GrantfromNokiaCompany 

出 版 物：《Journal of Southeast University(English Edition)》 (东南大学学报（英文版）)

年 卷 期：2004年第20卷第2期

页      码：135-138页

摘      要：A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.

主 题 词：multiple-input multiple-output (MIMO) chip-level interference minimum mean square error (MMSE) weight space-time equalization 

学科分类：080904[080904] 0810[工学-土木类] 0809[工学-计算机类] 08[工学] 080402[080402] 0804[工学-材料学] 081001[081001] 

核心收录：

D　O　I：10.3969/j.issn.1003-7985.2004.02.001

馆 藏 号：203244478...