Design and optimization for multiprocessor interactive GPU

作     者：DENG Jun-yong LI Tao JIANG Lin HAN Jun-gang SHEN Xu-bang 

作者机构：School of Micro-electronics Xidian University School of Electronic Engineering Xi’an University of Posts and Telecommunications 

基　　金：supported by the Key National Natural Science Foundation of China under Grant No.61136002 the National Natural Science Foundation of China under Grant No.61272120 the Natural Science Basic Research Plan in Shaanxi Province of China under Grant No.2013JC2-32 

出 版 物：《The Journal of China Universities of Posts and Telecommunications》 (中国邮电高校学报（英文版）)

年 卷 期：2014年第21卷第3期

页      码：85-97页

摘      要：In order to achieve maximization of parallelism, effective distribution of rendering tasks, balance between performance and flexibility in graphics processing pipeline, this article presents design, performance analysis and optimization for multi-core interactive graphics processing unit （MIGPU）. This processor integrates twelve processing cores with specific instruction set architecture and many sophisticated application-specific accelerators into a 3D graphics engine. It is implemented on XC6VLX550T field programmable gate array （FPGA）. MIGPU supports OpenGL2.0 with programmable front-end processor, vertex shader, plane clipper, geometry transformer, three-D clippers and pixel shaders. For boosting the performance of MIGPU, the relationship model is established between primitive types, vertices, pixels, and the effect of culling, clipping, and memory access, and shows a way to improve the speed up of the graphics pipeline. It is capable of assigning graphics rendering tasks to different processors for efficiency and flexibility. The pixel filling rate can reach to 40 Mpixel/s at its peak performance.

主 题 词：multiprocessor graphics processing unit (GPU) performance optimization parallelism 

学科分类：08[工学] 081201[081201] 0812[工学-测绘类] 

核心收录：

D　O　I：10.1016/S1005-8885(14)60305-8

馆 藏 号：203246020...