A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

作     者：CHENJianWu WUDanYU ZHOULei WUJin JINZhi LIUXinYu 

作者机构：Institute ofMicroelectronics Chinese Academy ofScienees Beijing 100029 China Key Laboratory of Microelectronics Devices ＆ Integrated Technology Institute of Microelectronics Chinese Academy of S~＇iences Betjing 100029 China 

基　　金：supported by the National Basic Research Program of China (2010CB327505) 

出 版 物：《Chinese Science Bulletin》 (中国科学通报)

年 卷 期：2012年第57卷第19期

页      码：2480-2487页

摘      要：A 32-bit pipeline accumulator with carry ripple topology is implemented for direct digital frequency *** increase the throughout while hold down the area and power consumption,a method to reduce the number of the pre-skewing registers is *** number is reduced to 29% of a conventional pipeline *** propagation delay versus bias current of the adder circuit with different size transistors is *** analyze the delay by employing the open circuit time constant *** to the simulation results,the maximum error is less than 8%.A method to optimum the design of the adder based on the propagation delay is *** clock traces for the 32-bit adder are heavily loaded,as there are 40 registers being connected to ***,the differential clock traces,which are much longer than the critical length,should be treated as transmission *** a clock distribution method and a termination scheme are proposed to get high quality and low skew clock signals.A multiple-type termination scheme is proposed to match the transmission line *** 32-bit accumulator was measured to work functionally at 5.3 GHz.

主 题 词：直接数字频率合成器 累加器 32位 设计 传播延迟 差分时钟 加法器 偏置电流 

学科分类：080902[080902] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.1007/s11434-012-5157-4

馆 藏 号：203248692...