A power-aware code-compression design for RISC/VLIW architecture

作     者：Che-Wei LIN Chang Hong LIN Wei Jhih WANG 

作者机构：Department of Electronic Engineering National Taiwan University of Science and Technology Taiwan 106 Taipei 

基　　金：Project (No.97-2218-E-011-016-) supported by the National Science Council 

出 版 物：《Journal of Zhejiang University-Science C(Computers and Electronics)》 (浙江大学学报C辑（计算机与电子（英文版）)

年 卷 期：2011年第12卷第8期

页      码：629-637页

摘      要：We studied the architecture of embedded computing systems from the viewpoint of power consumption in memory systems and used a selective-code-compression (SCC) approach to realize our *** on the LZW (Lempel-Ziv-Welch) compression algorithm,we propose a novel cost effective compression and decompression *** goal of our study was to develop a new SCC approach with an extended decision policy based on the prediction of power *** decompression method had to be easily implemented in hardware and to collaborate with the embedded *** hardware implementation of our decompression engine uses the TSMC 0.18μm-2p6m model and its cell-based *** calculate power consumption more accurately,we used a static analysis method to estimate the power overhead of the decompression *** also used variable sized branch blocks and considered several features of very long instruction word (VLIW) processors for our compression,including the instruction level parallelism (ILP) technique and the scheduling of *** code-compression methods are not limited to VLIW machines,and can be applied to other kinds of reduced instruction set computer (RISC) architecture.

主 题 词：LZW compression Cell-based libraries Instruction level parallelism (ILP) VLIW processors 

学科分类：0810[工学-土木类] 08[工学] 0805[工学-能源动力学] 081201[081201] 0812[工学-测绘类] 

核心收录：

D　O　I：10.1631/jzus.C1000321

馆 藏 号：203333947...