A 2 .5Gb/s GaAs MESFET Clock Recovery and Decision Circuit

作     者：詹琰 夏冠群 王永生 赵建龙 朱朝嵩 

作者机构：中国科学院上海冶金研究所上海200050 

基　　金：九五"科技攻关和国家自然科学基金 (批准号 :696760 0 3 ) 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2001年第22卷第7期

页      码：944-946页

摘      要：A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber *** circuit consists of a clock recovery circuit,including a preprocessor,phase detector(PD),low pass filter(LPF) and voltage controlled oscillator(VCO) and a decision circuit,including a comparator and a *** SPICE simulation result confirms the high frequency 2 5GHz of the clock recovery and the high speed 2 5Gb/s of the decision *** 2 5Gb/s decision circuit has proved to be able to deal with the input signal and produce a digital output signal after it being sampled by a clock signal.

主 题 词：GaAs MESFET clock recovery decision 

学科分类：080903[080903] 0809[工学-计算机类] 08[工学] 080501[080501] 0805[工学-能源动力学] 080502[080502] 

核心收录：

D　O　I：10.3969/j.issn.1674-4926.2001.07.026

馆 藏 号：203432530...