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Efficient multiuser detector based on box-constrained deregularization and its FPGA design

Efficient multiuser detector based on box-constrained deregularization and its FPGA design

作     者:Zhi Quan Jie Liu 

作者机构:Department of Electrical EngineeringFederal University of Juiz de ForaJuiz de Fora 36036900Brazil School of Information EngineeringDepartment of Electronic Information EngineeringZhengzhou UniversityZhengzhou 450001P.R.China RF Engines LimitedNewport PO305WBUK 

基  金:supported by the National Council for Technological and Scientific Development of Brazil (RN82/2008) 

出 版 物:《Journal of Systems Engineering and Electronics》 (系统工程与电子技术(英文版))

年 卷 期:2012年第23卷第2期

页      码:179-187页

摘      要:Multiuser detection can be described as a quadratic optimization problem with binary constraint. Many techniques are available to find approximate solution to this problem. These tech- niques can be characterized in terms of complexity and detection performance. The "efficient frontier" of known techniques include the decision-feedback, branch-and-bound and probabilistic data association detectors. The presented iterative multiuser detection technique is based on joint deregularized and box-constrained so- lution to quadratic optimization with iterations similar to that used in the nonstationary Tikhonov iterated algorithm. The deregulari- zation maximizes the energy of the solution, this is opposite to the Tikhonov regularization where the energy is minimized. However, combined with box-constraints, the deregularization forces the solution to be close to the binary set. We further exploit the box- constrained dichotomous coordinate descent (DCD) algorithm and adapt it to the nonstationary iterative Tikhonov regularization to present an efficient detector. As a result, the worst-case and aver- age complexity are reduced down to K28 and K2~ floating point operation per second, respectively. The development improves the "efficient frontier" in multiuser detection, which is illustrated by simulation results. Finally, a field programmable gate array (FPGA) design of the detector is presented. The detection performance obtained from the fixed-point FPGA implementation shows a good match to the floating-point implementation.

主 题 词:multiuser detection dichotomous coordinate descent (DCD) box-constrained DCD deregularization Tikhonov regular- ization low complexity field-programmable gate array (FPGA). 

学科分类:11[军事学] 0810[工学-土木类] 1105[1105] 080902[080902] 0809[工学-计算机类] 08[工学] 081002[081002] 110503[110503] 

核心收录:

D O I:10.1109/JSEE.2012.00023

馆 藏 号:203434875...

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