Quasi-Static Energy Recovery Logic with Single Power-Clock Supply

作     者：李舜 周锋 陈春鸿 陈华 吴一品 Li Shun;Zhou Feng;Chen Chunhong;Chen Hua;Wu Yipin

作者机构：复旦大学专用集成电路与系统国家重点实验室上海201203 温莎大学电子与计算机工程系 

基　　金：国家自然科学基金资助项目(批准号:90307008) 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2007年第28卷第11期

页      码：1729-1734页

摘      要：This paper presents a new quasi-static single-phase energy recovery logic （QSSERL）, which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control volta- ges. This not only ensures lower energy dissipation, but also simplifies the clock design, which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. Simulation with an 8bit logarithmic look- ahead adder （LLA） using static CMOS,clocked CMOS adiabatic logic （CAL,an existing typical single-phase ener- gy recovery logic）,and QSSERL,under 128 randomly generated input vectors,shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10MHz, and the QS- SERL adder achieves better energy efficiency than CAL when the input frequency finput is larger than 2MHz.

主 题 词：energy recovery adiabatic logic low power digital CMOS VLSI 

学科分类：080903[080903] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.3969/j.issn.1674-4926.2007.11.012

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