Architectural Design of 32 Bit Polar Encoder

作     者：G. Indumathi V. P. M. B. Aarthi Alias Ananthakirupa M. Ramesh G. Indumathi;V. P. M. B. Aarthi Alias Ananthakirupa;M. Ramesh

作者机构：Department of Electronics and Communication Engineering Mepco Schlenk Engineering College Sivakasi India Department of Electronics and Communication Engineering Kamaraj College of Engineering and Technology Virudhunagar India 

出 版 物：《Circuits and Systems》 (电路与系统（英文）)

年 卷 期：2016年第7卷第5期

页      码：551-561页

摘      要：The rapid development in the digital circuit design enhances the applications on very large scale integration era. Encoders are one among the digital circuits found in all communication systems. The polar encoding is mainly meant for its channel achieving property. It finds its application in communications, sensing and information theory. This coding proposed by Erdal Arikan is significant because of its zero error floors and simple architecture for hardware implementation. In this paper, a folded polar encoder is designed to start from the fully parallel architecture and proceeds with its data flow graph, delay requirement calculation, lifetime analysis and register allocation, which results in a very large scale integration architecture with minimum hardware utilization. The results are simulated for 4 and 8 parallel folded 32-bit polar encoder using Xilinx 14.6 ISIM and implemented in Virtex 5 field programmable gate array. A comparison is made on fully parallel and various folding techniques based on their resource utilization.

主 题 词：Polar Encoder Folding Very Large Scale Integration (VLSI) Architecture Field Programmable Gate Array (FPGA) 

学科分类：0809[工学-计算机类] 08[工学] 

D　O　I：10.4236/cs.2016.75047

馆 藏 号：203459118...