Design and simulation of a standing wave oscillator based PLL

作     者：Wei ZHANG You-de HU Li-rong ZHENG 

作者机构：State Key Lab of ASIC & SystemFudan University Pack Vinn Excellence CenterSchool of ICTRoyal Institute of Technology (KTH) Eletrum 229 

出 版 物：《Frontiers of Information Technology & Electronic Engineering》 (信息与电子工程前沿（英文版）)

年 卷 期：2016年第17卷第3期

页      码：258-264页

摘      要：A standing wave oscillator(SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor(IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop(PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9 M complementary metal-oxide-semiconductor(CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

主 题 词：Standing wave oscillator (SWO) Clock distribution Phase locked loop (PLL) Varactor 

学科分类：0810[工学-土木类] 080904[080904] 0808[工学-自动化类] 0809[工学-计算机类] 0839[0839] 08[工学] 0835[0835] 0812[工学-测绘类] 

核心收录：

D　O　I：10.1631/FITEE.1500210

馆 藏 号：203628636...