Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS

作     者：程龙 朱瑜 朱凯 陈迟晓 任俊彦 

作者机构：State Key Laboratory of ASIC & SystemFudan University Emensa Technology Co.Ltd 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2013年第34卷第10期

页      码：121-127页

摘      要：A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm^2.

主 题 词：DAC triple-channel digital-to-analog high speed 40 nm CMOS video DAC 

学科分类：080902[080902] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.1088/1674-4926/34/10/105007

馆 藏 号：203689098...