Cache Coherency Design in Pentium Ⅲ SMP System
作者机构：Key Laboratory of Data Storage System Huazhong University of Science and Technology Wuhan 430074 Hubei China
基 金：SupportedbytheNationalNaturalScienceFoundationofChina(60273074)
出 版 物：《Wuhan University Journal of Natural Sciences》 (武汉大学学报（自然科学英文版）)
年 卷 期：2006年第11卷第2期
页 码：360-364页
摘 要：This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transaction. Secondly it analyzes hardware snoopy mechanism of P6 bus and MESI state transitions adopted by Pentium Ⅲ. Based on these, it focuses on how muhiprocessors and the P6 bus cooperate to ensure cache coherency of the whole system, and gives the key of cache coherency design.
主 题 词：snoop cache coherency MESI protocol P6bus Pentium Ⅲ SMP system
学科分类：12[管理学] 1201[管理学-管理科学与工程类] 08[工学] 081201[081201] 0812[工学-测绘类]
核心收录：
D O I：10.1007/BF02832122
馆 藏 号：203757610...
