Design of ternary clocked adiabatic static random access memory

作     者：汪鹏君 梅凤娜 

作者机构：Institute of Circuits and SystemsNingbo University 

基　　金：Project supported by the National Natural Science Foundation of China(No.61076032) the Key Project of Zhejiang Provincial Natural Science of China(No.Z1111219) the K.C.Wong Magna Fund in Ningbo University,China 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2011年第32卷第10期

页      码：147-151页

摘      要：Based on multi-valued logic,adiabatic circuits and the structure of ternary static random access memory （SRAM）,a design scheme of a novel ternary clocked adiabatic SRAM is *** scheme adopts bootstrapped NMOS transistors,and an address decoder,a storage cell and a sense amplifier are charged and discharged in the adiabatic way,so the charges stored in the large switch capacitance of word lines,bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary *** PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power *** with ternary conventional SRAM,the average power consumption of the ternary adiabatic SRAM saves up to 68%in the same conditions.

主 题 词：multi-valued logic adiabatic ternary SRAM circuit design 

学科分类：08[工学] 081201[081201] 0812[工学-测绘类] 

核心收录：

D　O　I：10.1088/1674-4926/32/10/105010

馆 藏 号：203801620...