Reconfigurable implementation of AES algorithm IP core based on pipeline structure

作     者：李冰 夏克维 梁文丽 Li Bing;Xia Kewei;Liang Wenli

作者机构：东南大学集成电路学院南京210096 

出 版 物：《Journal of Southeast University(English Edition)》 (东南大学学报（英文版）)

年 卷 期：2010年第26卷第1期

页      码：21-25页

摘      要：In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.

主 题 词：advanced encryption standard (AES) algorithm reconfigurable pipeline finite field round transformation 

学科分类：07[理学] 08[工学] 070104[070104] 081101[081101] 0701[理学-数学类] 0811[工学-水利类] 

核心收录：

D　O　I：10.3969/j.issn.1003-7985.2010.01.005

馆 藏 号：203810404...