A reconfigurable computing architecture for 5G communication

作     者：GUO Yang LIU Zi-Jun YANG Lei LI Huan WANG Dong-lin 郭阳;刘子君;杨磊;李桓;王东琳

作者机构：Institute of AutomationChinese Academy of SciencesBeijing 100190China University of Chinese Academy of SciencesBeijing 100049China 

基　　金：Project(XDA-06010402)supported by the Strategic Priority Research Program of Chinese Academy of Sciences Project(Y5S7061G51)supported by the Youth Innovation Promotion Association of Chinese Academy of Sciences 

出 版 物：《Journal of Central South University》 (中南大学学报（英文版）)

年 卷 期：2019年第26卷第12期

页      码：3315-3327页

摘      要：5G baseband signal processing places greater real-time and reliability requirements on *** on the architecture of the MaPU,a reconfigurable computing architecture is proposed according to the characteristics of the 5G baseband signal processing.A dedicated instruction set for 5G baseband signal processing is *** corresponding functional units are designed for reuse of hardware resources.A redirected register file is proposed to address latency and power consumption issues in internetwork.A two-dimensional code compression scheme is proposed for cases in which the use ratio of instruction memory is *** access mode of the data memory is extended,the performance is improved and the power consumption is *** throughput of 5G baseband processing algorithm is one to two orders of magnitude higher than that of the TMS320C6670 with less power *** silicon area evaluated by layout is 5.8 mm2,which is 1/6 of the MaPU’*** average power consumption is 0.7 W,which is 1/5 of the MaPU’s.

主 题 词：5G communication instruction set register file code compression throughput power consumption 

学科分类：08[工学] 0812[工学-测绘类] 

核心收录：

D　O　I：10.1007/s11771-019-4255-8

馆 藏 号：203871726...