Universal trench design method for a high-voltage SOI trench LDMOS

作     者：胡夏融 张波 罗小蓉 李肇基 

作者机构：State Key Laboratory of Electronic Thin Films and Integrated DevicesUniversity of Electronic Science and Technology of China 

基　　金：supported by the National Natural Science Foundation of China(Nos.61176069,60976060) the National Key Laboratory of Analogue Integrated Circuit,China(No.9140C090304110C0905) 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2012年第33卷第7期

页      码：47-50页

摘      要：The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage （BV） and specific on-resistance （Rs, on） into account. The high-k （relative permittivity） dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs, on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

主 题 词：SOI trench permittivity RESURF LDMOS breakdown voltage 

学科分类：080903[080903] 0808[工学-自动化类] 0809[工学-计算机类] 08[工学] 080501[080501] 0805[工学-能源动力学] 080502[080502] 0703[理学-化学类] 0702[理学-物理学类] 

核心收录：

D　O　I：10.1088/1674-4926/33/7/074006

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