An efficient hardware design for HDTV H.264/AVC encoder

作     者：Liang WEI 

作者机构：Institute of Information and Communication Engineering Zhejiang University Hangzhou 310027 China Zhejiang Provincial Key Laboratory of Information Network Technology Hangzhou 31002 7 China 

基　　金：supported by the National Natural Science Foundation of China (No. 61076021) the Program for New Century Excellent Talents in Universities, China 

出 版 物：《Journal of Zhejiang University-Science C(Computers and Electronics)》 (浙江大学学报C辑（计算机与电子（英文版）)

年 卷 期：2011年第12卷第6期

页      码：499-506页

摘      要：This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.

主 题 词：H.264/AVC High-definition television (HDTV) Hardware Architecture Encoder 

学科分类：0810[工学-土木类] 08[工学] 0805[工学-能源动力学] 081001[081001] 0812[工学-测绘类] 

核心收录：

D　O　I：10.1631/jzus.C1000201

馆 藏 号：203910511...