Multi-seed-encoding BIST Design with Low Power Consumption Based on the Folding Counter

作     者：刘建军 潘学文 

作者机构：School of Information Engineering Jimei University xiamen 361021 China School of Computer Communication Engineering Hunan University of Science and Engineering Yongzhou 425100 China 

基　　金：supported by General Equipments Ministry for the Fore-research of Military Electronic Devices Technology in the 11th Five Plan(No.51323030406) 

出 版 物：《Journal of Measurement Science and Instrumentation》 (测试科学与仪器（英文版）)

年 卷 期：2010年第1卷第3期

页      码：276-280页

摘      要：In this paper, by using the folding counter and linear feedback shift register, a new vector generator is proosed. The decisive testing patterns are generated by using the selected fold distance. Then the folding counter seeds are encoded by the specialized seed encoder and clock gating, the ineffective patterns do not act upon the circuit under test, these testing patterns are designed to form a pseudo single input change set, so as to lead to prominent decreases in power consumption and redundant testing patterns generated by different seeds, without losing stuck-at fault coverage. Experimental results based on ISCAS＇85 benchmark circuits demonstrate the efficiency of the approach.

主 题 词：Folding counter pseudo single power consumption 

学科分类：08[工学] 081201[081201] 0812[工学-测绘类] 

D　O　I：10.3969/j.issn.1674-8042.2010.03.16

馆 藏 号：203995094...