A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS

作     者：张长春 王志功 施思 潘海仙 郭宇峰 黄继伟 Zhang Changchun;Wang Zhigong;Shi Si;Pan Haixian;Guo Yufeng;Huang Jiwei

作者机构：东南大学射频与光电集成电路研究所南京210096 东南大学生物电子学国家重点实验室南京210096 

基　　金：The National High Technology Research and Development Program of China (863 Program)(No. 2007AA01Z2a5) the National Natural Science Foundation of China (No. 60806027,61076073) Specialized Research Fund for the Doctoral Program of Higher Education (No.20090092120012) 

出 版 物：《Journal of Southeast University(English Edition)》 (东南大学学报（英文版）)

年 卷 期：2011年第27卷第2期

页      码：136-139页

摘      要：In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

主 题 词：clock recovery phase frequency detector voltagecontrolled oscillator phase noise 

学科分类：0810[工学-土木类] 07[理学] 08[工学] 0805[工学-能源动力学] 0812[工学-测绘类] 

核心收录：

D　O　I：10.3969/j.issn.1003-7985.2011.02.004

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