Design of an unbuffered switch for network on-chip

作     者：刘浩 Cao Feifei Zhou Ning Zou Xuecheng Liu Dongsheng 

作者机构：Henan Electric Power Research Institute Henan Electric Power Industrial School Department of Electronic Science & TechnologyHuazhong University of Science & Technology 

基　　金：Supported by the National High Technology Research and Development Program of China(No.2009AA01Z105) the Ministry of EducationIntel Special Foundation for Information Technology(No.MOE-INTEL-08-05) the Postdoctoral Science Foundation of China(No.20080440942,200902432) 

出 版 物：《High Technology Letters》 (高技术通讯（英文版）)

年 卷 期：2013年第19卷第1期

页      码：24-29页

摘      要：In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication *** regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication *** paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch *** to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so *** synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.

主 题 词：网络芯片 缓冲机 开关 设计 交换架构 芯片系统 互连网络 通信性能 

学科分类：080903[080903] 0809[工学-计算机类] 08[工学] 

核心收录：

D　O　I：10.3772/j.issn.1006-6748.2013.01.005

馆 藏 号：203996311...