摘要：利用小信号压控电流源(VCCS)电路产生所需零点,是一种先进的低压降稳压器(LDO)频率补偿方法。文章分析了VCCS频率补偿方法的原理和VCCS电路对LDO的瞬态响应及电源抑制(PSR)特性的改善作用,并提出了一种新的VCCS电路结构。该电路结构功耗低、占用面积小,在直到5 MHz的频率范围内,都有近乎理想的性能。采用这种结构的VCCS电路,基于0.5μm CMOS工艺,设计的一款300 mV压降,2.5 V输出电压,最大100 mA输出电流的LDO电路,具有很好的频率响应、瞬态响应和电源抑制特性。该LDO电路所用全部片上电容的总值不到1pF。

摘要：A high-accuracy,low-dropout （LDO） voltage regulator is presented. Using the slow-rolloff frequency compensation scheme, the LDO effectively overcomes the stability problem, facilitates the use of a ceramic capacitor, and improves the output voltage accuracy, which is critical for powering high-performance analog circuitry. The slow-rolloff compensation scheme is realized by introducing three pole-zero pairs, including the proposed polezero pair and sense zero. The post-layout simulation results demonstrate that this LDO has robust system stability, a high open-loop gain, and a high unit-gain frequency,which lead to excellent regulation and transient response performance. The line and load regulation are 27μV/V and 3.78μV/mA, and the overshoots of the output voltage are less than 30mV,while the dropout voltage is 120mV for a 150mA load current.