摘要：深入研究了静电感应晶闸管的开通时间、关断时间,它们受空穴存贮时间、栅宽、n-区的厚度、阳极电流及栅极抽出的峰值电流的影响,在工艺中需要折衷考虑。研究结果对于静电感应器件,特别是对于静电感应晶闸管的设计和制造有一定的实用价值。

摘要：介绍了电容脉冲测试原理,指出采用高电压、小电流的直流电源,可对电力SITH的动态参数进行模拟测试.文中给出了测试电路的设计计算方法.

摘要：提出了一种新型结构的静电感应器件,设计了一道环绕的深槽,用以切断寄生效应.静电感应器件的寄生效应会导致器件性能的劣化甚至失效,文中提出了寄生效应的模型,并用PSPICE进行了仿真模拟,数值模拟结果和实验结果一致.实验表明这种深槽结构能够有效截断寄生路径,消除寄生电流的影响,优化器件性能.同时,文章详细描述了这种器件的设计和制造工艺.

摘要：用磨角法测量扩散结深和横向扩散比例将遇到来自两方面的误差影响：斜角的影响和结面交连的影响。斜角的影响是主要的但往往被忽视，结面交连的影响在两结十分靠近且结深较大时比较明显，对于静电感应器件而言更是如此，二者均使测量结果的误差和数据的离散性偏大。斜角的影响表现在使测得的横向扩散比例减小，甚至是成倍地减小。结面交连的影响是在结深较大时使测得的横向宽度长度实际上与纵向深度无关，得到的横向扩散比例随纵向结深反比例地减小。这些误差将会使器件的设计和工艺调节失去基础。横向扩散比例的异常变化并不意味着扩散动力学新效应。

摘要：The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are *** effects of parasitic gate-source capacitance (C gs) on the power performance of SIT are *** main methods and considerations to diminish C gs,consequently to improve the high power performance are *** epitaxy technology is the critical step to decrease C *** 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.

摘要：The mixed non-saturating I-V characteristics of static induction transistor (SIT) are *** optimum matching relations among the structural,material,and technological parameters are also *** technological experiments demonstrate that the channel parameters play a critical role in determining whether it is a mixed,triode-like or pentode-like I-V *** general control principles,methods,and criterions of fabrication parameters as well as the effect of control factor are analytically *** results are useful for design and fabrication of SIT,especially for SIT with mixed I-V characteristics.

摘要：Methods for improving the high current performance of static induction transistor （SIT） are *** important factors,such as ＂trans-conductance per unit channel width＂ θ, ＂gate efficiency＂ η, ＂sensitivity factor＂ D,and ＂intrinsic static gain＂ μ0,that may be used to describe different aspects of the electrical performance of an SIT are first *** dependences of electrical parameters on the structure and technological process of an SIT are revealed for the first *** packaging technologies are so important for the improvement of high power performance of SITs that they must be paid *** techniques and circuits for measuring frequency and power parameters of SITs are designed and *** influence of packaging processes in technological practice on the electrical performance of SITs is also discussed in depth.

摘要：讨论了电力静电感应晶闸管的主要电参数与器件结构的关系，以及电参数的工艺调节。设计了１００Ａ／１２００Ｖ的器件并给出了研制结果。

摘要：首先对ＳＩＴＨ正向通态和阻断态的Ｉ－Ｖ特性给出了物理考察和解释。然后通过解析方法得到了ＳＩＴＨ沟道的电势分布，在此基础上，用有限差分法和迭代法求解了精确的沟道电势，得到了马鞍状的势分布，进而研究了沟道势垒随偏压的变化。发现栅压对沟道势垒的控制是直接而灵敏的，为栅极强迫关断提供了物理基础，所得结果可使我们对ＳＩＴＨ作用机制的理解更加清楚，同时为器件的设计制造提供了参考依据。

摘要：从理论和实验两方面对静电感应晶体管（ＢＳＩＴ）的开关时间进行了分析和测量，提出了简单的分析方法，将影响ＢＳＩＴ开关时间的各个因素归结为结构因子和材料因子，从而简化了分析影响ＢＳＩＴ开关时间的因素，对于ＢＳＩＴ的实际工艺、结构设计有指导意义。