摘要：介绍了用于SDH系统STM-64速率光发射机用的激光二极管/光调制器驱动器集成电路的设计。电路采用法国OMMIC公司的0.2μm GaAs PHEMTs工艺设计并制造,可以驱动激光二极管和电吸收式调制器。电路由输入匹配电路、预放大电路、源极跟随器、主放大电路、电容耦合电流放大器和输出电路组成。电路芯片面积1.0mm×0.9mm。测试结果表明,电路采用单一正5V电源供电,直流功耗1.4W,可以在10Gb/s速率下正常工作,眼图良好。最高工作速率高于20Gb/s,输出电压幅度2.8V。

摘要：利用CMOS工艺设计的功率放大器具有制造成本低的优点。介绍一种使用中芯国际(SMIC)公司0.18μmCMOS工艺设计的A类功率放大电路。采用单端两级放大,结构简单并且能够稳定工作。该功率放大器中心工作频率为2.4GHz。电路用Cadence公司的SpectreRF工具进行模拟,1dB压缩点输出功率22dBm,最大输出功率24dBm,可应用于蓝牙系统发射模块。

摘要：Based on the 4-channel neural signal regeneration system which is realized by using discrete devices and successfully used for in-vivo experiments on rats and rabbits, a single channel neural signal regeneration integrated circuit （IC）is designed and realized in CSMC ＇ s 0. 6 μm CMOS （ complementary metal-oxide-semiconductor transistor ） technology. The IC consists of a neural signal detection circuit with an adjustable gain, a buffer, and a function electrical stimulation （FES） circuit. The neural signal regenerating IC occupies a die area of 1.42 mm × 1.34 mm. Under a dual supply voltage of ±2. 5 V, the DC power consumption is less than 10 mW. The on-wafer measurement results are as follows： the output resistor is 118 ml）, the 3 dB bandwidth is greater than 30 kHz, and the gain can be variable from 50 to 90 dB. The circuit is used for in-vivo experiments on the rat＇ s sciatic nerve as well as on the spinal cord with the cuff type electrode array and the twin-needle electrode. The neural signal is successfully regenerated both on a rat＇ s sciatic nerve bundle and on the spinal cord.

摘要：知识产权文化建设提供了全球一体化下形成和谐知识产权秩序的一个新思路和途径。知识产权文化建设的具体目标应分解到制度形态和观念形态两个层面的建设上,并且要针对中国传统文化的具体现实设计中国的实践措施。

摘要：A low-power, high-gain circuit for function electrical stimulation （FES） is designed for the microelectronic neural signal regeneration system based on CSMC （CSMC Technologies Corporation） 0. 6μm CMOS （complementary metal-oxide-semiconductor transistor） technology. It can be used to stimulate microelectrodes connected with the nerve bundles to regenerate neural signals. This circuit consists of two stages： a full differential folded-cascode amplifier input stage and a complementary class-AB output stage with an overload protection circuit. The rail-to-rail input and output stages are used to ensure a wide range of input and output voltages. The simulation results show that the gain of the circuit is 81 dB; the 3 dB-bandwidth is 295 kHz. The chip occupies a die area of 1.06 mm × 0. 52 mm. The on-wafer measurement results show that under a single supply voltage of ＋ 5 V, the DC power consumption is about 7. 5 mW and the output voltage amplitude is 4. 8 V. The chip can also mn well under single supply voltage of ＋ 3.3 V.

摘要：采用0.2μmGaAsPHEMT工艺设计并实现了超高速光纤通信系统用激光二极管/调制器集成驱动器电路.整个电路由带源极跟随器的两级差分放大电路、电容耦合电流放大器和输出电路组成.电路芯片面积为1.0mm×0.9mm.测试结果表明,采用单一+5V电源供电时直流功耗为1.5W,输出最高电压幅度为2.4V,电路最高工作速率高于24Gb/s,可以应用于光纤通信SDH(synchronous digitalhierarchy)传输系统.

摘要：设计并实现了一种应用于中枢神经信号重建系统中的跨导放大器。采用前馈结构,有效地减小了输入失调电压,并提高了对共模信号的抑制能力,且电压输入范围允许自正电源电压至负电源电压。输出电流最高可达1mA。电路采用0.6μm CMOS工艺制造,面积0.6mm2。测试得到的电路跨导为0.38mS,输入失调电压为0.57mV,共模抑制比为-54dB,可满足中枢神经信号重建系统的要求。

摘要：A low-power IC for function electrical stimulation （FES） of nerves is designed for an implantable system and fabricated in CSMC＇s 0.6μm CMOS technology. The IC can be used for stimulating animals＇ spinal nerve bundles and other nerves connected with a cuff type electrode. It consists of a pre-amplifier,a main amplifier,and an output stage. According to the neural signal spectrum,the bandwidth of the FES signal generator circuit is defined from 1Hz to 400kHz. The gain of the circuit is about 66dB with an output impedance of 900. The 1C can function under a single supply voltage of 3-5V. A rail-to-rail output stage helps to use the coupled power efficiently. The measured time domain performance shows that the bandwidth and the gain of the IC agree with the design. The power consumption is lower than 6mW.

摘要：随着我国老年社会的来临,老年人的居住环境日益引起人们的重视和关注。受历史客观条件的限制,我国在老年人住宅设计方面缺乏专门的研究与实践,给老年人的生活带来不良影响。本文针对老年人生理心理特点,提出应以人为本的设计理念,供参考。

摘要：科技的不断进步将我们带入到信息时代。在建筑结构设计领域,计算机设计软件随科技的发展不断更新,功能不断完善,给广大建筑结构工程师的设计工作带来了前所未有的便利和快捷。在实践中结构工程师不能正确对待设计软件的使用问题,给建筑设计带来隐患。本文对此作了分析并提出应对方法。