摘要：三管有源像素因其像素面积小、填充因子高,是应用最广泛的一种像素结构.填充因子对像素的特性影响很大.增大像素的填充因子可以增加像素的灵敏度和信噪比,但增加像素的面积会限制像素可以达到的最大分辨率,因此像素设计一般是在确定像素尺寸和工艺的情况下,最大限度地提高填充因子.本文在详细分析CIS三管有源像素结构的基础上,采用NMOS复位管和共源共栅结构的源随器偏置管的组合结构,设计出一种高填充率的CIS三管有源像素,填充率达到57%.通过仿真和单元测试,证明方案有效.

摘要：基于SMIC 0.18μm工艺设计了一种低噪声的四管像素结构.通过在像素内增加传输管和存储节点实现了相关双采样,可同时消除固定模式噪声和随机噪声;采用Pinned光电二极管技术大幅降低了表面暗电流.所设计像素尺寸为3.6μm×3.6μm,并将其应用于一款648×488像素阵列CMOS图像传感器,经流片测试,图像传感器信噪比可达42 dB,在25℃下表面暗电流为25 mV/s(转换成电压表示的).所设计的四管Pinned光电二极管像素结构相对于传统三管像素结构,具有较低的噪声和暗电流.

摘要：A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

摘要：针对用于电池管理系统中数模转换器的高精度要求以及Sigma-Delta ADC的适用特点,提出了一种加入零点优化的单环三阶前馈调制器结构以及适用于本系统的低功耗数字滤波器模型,通过噪声传输函数设计三准则和信号频谱分析给出具体设计及仿真参数,经验证该模型达到系统所需16位有效分辨率要求且易于电路实现。

摘要：基于0.5μm工艺设计一种带软启动电路大摆幅输入电压的线性稳压源（LDO）,为解决高电压输入时LDO输出节点的瞬态过冲电流问题,设计一种在缓冲器的输出端加入MOS开关的软启动方案,提高电路的安全可靠性。通过仿真分析,结果表明该电路在输入电压10~40 V变化,其线性调整度为7.5 m V@30 V,输出5 V稳定电压,负载电流范围0~10 m A,输出电流1~10 m A,瞬态变化时负载调整度为12 m V@9 m A。电源电压上电时间为1 ms时,LDO的输出过充电流不超过6 m A。

摘要：采用Ｐ阱ＣＭＯＳ工艺设计并制作了一种模拟型的Ｈａｍｍｉｎｇ神经网络集成电路．测试结果表明，网络中的宏单元，模板匹配运算电路，可很好地实现容差匹配的功能．将芯片用作识别器，识别手写体阿拉伯数字的实验结果表明，可在５００ｎｓ内完成一次识别运算；对所采集的数据集得到了较好的识别效果．识别测试结果还表明，识别效果对控制参量阈值电压ＶＴ的变化较敏感．

摘要：Noise and mismatch are important error sources in pipeline ADCs,so careful calculation and system simulation are carried out using Matlab software. To reduce power consumption while not lose performance, the amplifiers with the same structure are biased with one bias circuit, and a cascode compensation is adopted. A 10bit 50MS/s pipeline ADC, which can be used in CMOS image sensor systems with large pixel array,is designed and tested by using 0.35tzm 4M-2P CMOS process. According to test results, power consumption is only 42mW and SINAD is 45.69dB when sampling frequency is 50MHz. A balance between performance and power consumption is achieved.

摘要：提出了用于运动补偿帧频提升的改进三步搜索,并描述了算法的系统实现。系统具有高度并行、实时性高等优点,经过FPGA系统验证,所处理的图像主观质量良好,满足应用需要。

摘要：从芯片采用的算法、兼容性和集成度3个方面对国内外视频格式转换主流芯片的性能特点进行分析对比,从而使读者对于视频格式转换芯片有一个系统的认识,并根据数字电视的发展趋势,展望了视频格式转芯片的发展方向。

摘要：A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and success-fully taped out with a Chartered 0.35μm process. The pixel pitch is 8μm × 8μm with a fill factor of 57%, the photo-sensitivity is 0.8V/（lux · s） ,and the dynamic range is 50dB. Theoretical analysis and test results indicate that as the process is scaled down, a smaller pixel pitch reduces the sensitivity. A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.