摘要：设计一种具有新型解调电路和安全功能的超高频RFID标签芯片。该解调电路不需要单独的包络检测电路,而是利用标签芯片已有的整流器的第一级作为包络检测电路。同时还设计了一种特殊的均值检测电路,输出电压和包络信号之间有很大的电压差,使得比较器的设计更加容易。受标签和读写器距离的变化影响,包络信号的直流电压在很大范围内变化,因此还设计了具有轨到轨共模输入范围的比较器。为了保证标签和读写器之间通信的安全,在数字基带处理器中集成了128位的高级加密标准算法(AES)。整个标签芯片采用0.18μm工艺实现,芯片面积为880μm×950μm。测试结果表明,标签芯片可以解调出的射频输入信号最小幅度为100 mV,最大的数据率为160 kb/s。

摘要：基于动态阈值补偿技术,提出了一种适用于无源超高频RFID标签的高效率整流电路。该整流电路可以根据MOS管的工作状态对MOS管阈值电压进行动态补偿,使得MOS管同时具有低的导通电压和反向泄漏电流,从而实现高的功率转换效率。采用该整流电路的无源超高频RFID标签芯片在0.18μm CMOS工艺下设计实现。测试结果表明,在驱动80kΩ负载时,整流电路的功率转换效率最高可达53.7%。相比于传统整流电路,转换效率提高了约20%。

摘要：A fully integrated passive UHF RFID tag complying with the ISO 18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm.

摘要：This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B *** tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM *** improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit *** of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband *** whole tag chip is implemented in a TSMC 0.18μm CMOS process with a die size of 800×800μm;. Measurement results show that the total power consumption of the tag chip is only 7.4μW with a sensitivity of -12 dBm.