摘要：设计了一款低功耗12bit 100MS/s流水线逐次逼近型模数转换器(Pipelined SAR ADC),提出了一种第二级子模数转换器时间交织的结构,改善了模数转换器的采样率;优化Pipelined SAR ADC前后级子ADC的位数关系,同时结合半增益运算放大器技术,降低了运放的设计难度,减小了运放的功耗.本设计是在TSMC65nm LP工艺下设计实现的,在电源电压为1.2V,采样率为100MS/s,输入信号为49.1MHz时,此ADC可达到69.44dB的信噪比(SNDR)和74.04dB的无杂散动态范围(SFDR),功耗为8.6mW.

摘要：This paper presents a 1.12 Gb/s 11.3 mW transmitter using 0.18μm mixed signal complementary metal- oxide semiconductor technology with a 1.8 V supply voltage. This transmitter implements a high-speed transmission with 1.2 V common-mode output voltage, adopting a low-voltage differential signaling （LVDS） technique. A multiplexer （MUX） and an LVDS driver are critical for a transmitter to complete a high-speed data transmission. This paper proposes a high power-efficiency single-stage 14 ： 1 MUX and an adjustable LVDS driver circuit, capable of driving different loads with a slight increase in power consumption. The prototype chip implements a transmitter with a core area of 970 × 560μm2, demonstrating low power consumption and adjustable driving capability.