摘要：研究了P埋层深度对体硅Triple-RESURF LDMOS纵向电场和击穿电压的影响。分析表明,当P型埋层靠近器件表面时,纵向电场平均值较小,击穿电压较低;当P型埋层靠近衬底时,优化漂移区浓度较低,器件比导通电阻较大;当P型埋层位于漂移区中部时,器件的BV2/Rs,on设计优值最大。指出了P型埋层在漂移区不同区域时击穿点的位置,以及对应的漂移区浓度取值范围,为横向高压Triple-RESURF LDMOS的设计提供了参考。

摘要：The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage （BV） and specific on-resistance （Rs, on） into account. The high-k （relative permittivity） dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs, on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.