摘要：介绍了正交解码与可逆计数通用芯片的主要工作原理,在此基础上主要通过对Agilent公司HCTL—2020的功能分析扩展了正交解码芯片对三路信号的处理能力,并完成了对各个模块的功能仿真。实验结果表明,该方案准确、可靠,有一定的抗干扰能性,适用的范围大。

摘要：详细介绍了手机用TFT彩色液晶显示驱动控制芯片内置GRAM的访问管理与地址控制,以及GRAM访问控制模块如何实现手机窗口显示以及动态图片数据高速写入等功能,并在此基础上给出了各功能的实现方案和电路设计,同时解决了GRAM访问时序冲突问题。

摘要：In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in space *** readout channel is comprised of a charge sensitive amplifier,a CR-RC shaping amplifier,an analog output buffer,a fast shaper,and a *** 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology,the die size of the prototype chip is 2.2×2.2 mm^*** input energy range is from 5 to 350 *** this 8-channel prototype ASIC,the measured electrical characteristics are as follows：the overall gain of the readout channel is 210 V/pC,the linearity error is less than 2%,the crosstalk is less than 0.36%,The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad,and the power consumption is less than 2.4 mW/*** the measurement together with a CdZnTe detector,the energy resolution is 5.9%at the 59.5-keV line under the irradiation of the radioactive source ^（241）*** radiation effect experiments show that the proposed ASIC can resist the total ionization dose（TID） irradiation of higher than200 krad（Si）.

摘要：分析了噪声以及器件失配对延迟锁相环的抖动影响,并对延迟锁相环的各模块进行了Verilog-A精确建模和性能仿真。仿真结果表明,器件失配对延迟链中间相输出的抖动影响最大,产生了约50ps的偏移;而噪声对延迟链最后一相输出的抖动影响最大,其peak-to-peak抖动值达到85ps。另外,与电路晶体管级仿真相比,通过Verilog-A建模节省了大量仿真时间,极大地提高了设计效率。