摘要：Since the dawn of the Internet of Things(IoT),data and system security has been the major concern for *** most IoT devices operate on 8-bit controllers with limited storage and computation power,encryption and decryption need to be implemented at the transmitting and receiving ends,respectively,using lightweight *** present novel architectures for hardware implementation for the ANU cipher and present results associated with each *** ANU cipher is implemented at 4-,8-,16-,and 32-bit datapath sizes on four different field-programmable gate array(FPGA)platforms under the same implementation condition,and the results are compared on every performance *** previous ANU architectures,the new architectures have parallel substitution boxes(S-boxes)for high throughput and hardware *** these different datapath designs,ANU cipher proves to be the obvious choice for implementing security in extremely resourceconstrained systems.