摘要：A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circu.t-board (rigid and or flexible) u.ed in baseband infrastru.tu.es. Indicated here is a way of adopting a planar fractal indu.tor configu.ation to improvise the necessary time-delay in the transits of digital signal phase jitter and redu.e the TIE. This paper addresses systematic design considerations on fractal indu.tor geometry commensu.ate with practical aspects of its implementation as delaylines in the high-speed digital transports at the baseband operations of smart-phone infrastru.tu.es. Experimental resu.ts obtained from a test modu.e are presented to illu.trate the efficacy of the design and acceptable delay performance of the test stru.tu.e commensu.ate with the digital transports of interest.