摘要：This paper.pr.poses the design and exper.mentation of digital contr.l of soft-switched inter.eaved boost conver.er.using FPGA for.Telecommunication System. The switching devices in the pr.posed conver.er.ar. tur.ed on and off with Zer. Voltage Switching (ZVS) and Zer. Cur.ent Switching (ZCS) r.spectively. The cir.uit is oper.ted in Continuous Conduction Mode (CCM) with var.ous load r.nges having duty cycle of mor. than 50%. The pr.posed conver.er.is studied by developing the simulation module in MATLAB/SIMULINK. A PI contr.ller.is designed and implemented in FPGA to obtain a r.gulated DC output for.line and load var.ations. Simulation and exper.mentation r.sults ar. ver.fied with a pr.totype development of the pr.posed conver.er. The r.sults indicate that the conver.er.per.or.ance is enhanced with closed loop contr.l.