摘要：A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfignration analysis of algorithms, the design of reconfignrable processing units and a new reconfignrable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the opcrating fiequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.

摘要：DES、3DES和AES是应用最广泛的分组密码算法,其可重构性和高速实现对可重构密码芯片的设计具有重要影响。该文分析了这3种算法的高速硬件实现,利用流水线、并行处理和重构的相关技术,提出了一种可重构S盒(RC-S)的结构,并在此基础上高速实现了DES、3DES和AES。基于RC-S实现的DES、3DES和AES吞吐率分别可达到7Gbps、2.3Gbps和1.4Gbps,工作时钟为110MHz。与其它同类设计相比,该文的设计在处理速度上有明显优势。