摘要：A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is *** supports SAW-less operation for *** improve the linearity in terms of both IP3 and IP2,the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization,current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs.A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle *** addition,a constant-g_m biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the *** RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13μm *** measurement results show that owing to this high-linearity RF front-end,the receiver achieves -6 dBm IIP3 and better than ＋60 dBm IIP2 for all modes and bands.

摘要：随着涡扇发动机涵道比的不断提高,风扇噪声对于发动机总噪声的贡献量越来越大,因此准确地预测风扇噪声对发动机的降噪设计和适航符合性评估具有重要的意义。在现有风扇噪声半经验预测模型架构的基础上,利用某型号大涵道比涡扇发动机的噪声试验数据,适应性地发展了风扇纯音噪声预测模型,将预测模型中的转/静间距函数与叶片后掠角及工况相关联,并提出考虑不同工况影响的指向性函数,预测精度较现有模型有大幅提升。与试验数据的对比表明,本模型的预测误差在5 dB之内,验证了新开发模型的准确性。

摘要：陶瓷基复合材料(ceramic matrix composites,CMC)涡轮动叶榫头是动叶装配与承受离心载荷的关键。为了研究熔渗工艺制备CMC榫头在叶片旋转径向拉伸载荷下的力学行为,验证榫头内部质量对其静拉伸强度与破坏模式的影响,设计并制备燕尾形CMC高压涡轮动叶榫头元件试件,对其进行单轴静态拉伸实验,采用X射线CT无损检测对实验前试件内部质量进行扫描,采用DIC与声发射方法对实验过程进行监测。结果表明:燕尾形CMC榫头在单轴静态拉伸下保持完好接触,其静态拉伸强度与破坏模式对其内部质量(尤其是分层缺陷)非常敏感。试件不含分层缺陷时,损伤起始于榫头颈部,并迅速扩展,损伤起始载荷与最大破坏载荷接近,断口呈横向锯齿状;试件内部含分层缺陷时,损伤起始于缺陷,分层逐渐扩展并导致试件断裂,损伤起始载荷下降99.05%,最大破坏载荷下降14.29%,断口位置与分层缺陷一致。

摘要：A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is *** the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward *** 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about *** indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

摘要：介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统.通过较准确地计算电路的直流工作点和MOS管的小信号参数,以及由电路拓扑结构自动生成电路性能公式对已有的基于公式的方法进行了改进;同时考虑了电路的可制造性问题,使得综合出的电路在工艺波动和工作条件变化时仍能满足性能要求.大量的实验结果表明:与基于模拟器的方法相比,采用该系统可以快速综合出可制造的深亚微米CMOS模拟单元电路.

摘要：在高精度平板显示系统中 ,传统的界面将液晶显示控制器直接与平板图像控制器连接。由于信号的并行满摆幅传输 ,该界面不能解决强电磁干扰及高功耗等问题。给出了一种基于ANSI/TIA/EIA - 6 44标准的低压差分信号 (LVDS)数据发送系统 ,以解决传统数字视频界面的瓶颈问题。该系统采用 0 18μmCMOS工艺进行设计。高速、较少的并行传输线及低电压摆幅等系统特性实现了高速、低功耗、低电磁干扰 ,单通道数据传输率 784Mb/s ,总数据传输率达 392Mb/s的高速数字视频信号的传输。满足了SVGA、XGA、SXGA等显示模式分辨率的要求。该数据发送器采用HSPICE仿真器在各种PVT情况下做了仿真 ,结果表明 ,系统的各项指标满足上述标准 ,部分参数优于标准的要求。

摘要：介绍了一种CMOS全差分两级OTA,第一级为折叠级联放大器,第二级为共源输出增益级,OTA技术采用了级联密勒电容补偿技术和开关电容共模反馈技术.在分析了OTA的零极点分布以及建立特性后,设计出一个MATLAB优化程序,找到最佳的阻尼因子和自然频率使OTA建立时间最小,并通过CadenceSpectre仿真表明,该OTA完全满足性能指标要求.

摘要：A fully integrated low power transmitter for an IEEE 802. llb transceiver system is implemented in SMIC 0.18μm technology. The direct-conversion transmitter includes two Chebyshev I low pass filters,two PGAs,a SSB mixer, and a PA driver. The transmitter provides a gain control of 32dB in 3dB steps. The maximum output power is - 3.4dBm and the EVM is 6. 8%. The power consumption of the transmitter is only 57.6mW with a 1.8V power supply. The chip area of the transmitter is 1.6mm × 1.6mm.

摘要：A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented. This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution. Five key blocks,i, e., a low noise amplifier （LNA）, a down-conversion mixer, a variable gain amplifier, a low pass filter, and a DC- offset cancellation circuit,are designed based on system design and low noise high linearity considerations. The necessary auxiliary circuits are also included. Fabricated in SMIC 0.18μm 1p6m RF CMOS process, the receiver＇s performance is measured as：4. 1 dB noise figure, - 7.5dBm input third order intercept point （IIP3） for LNA ＆ mixer at high gain setting, - 14dBm IIP3 for the whole receiver,53dBc @30MHz offset of adjacent channel power rejection,and less than 5mV out- put DC-offset. The receiver consumes 44mA under a 1.8V power supply with I,Q two paths.

摘要：A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.