摘要：目的为研究支撑-半刚接钢框架结构体系的抗震性能,方法设计了一榀由嵌套式单边螺栓与T型钢构成的半刚性梁柱节点的中心支撑钢框架,并进行了拟静力试验与有限元数值模拟,通过观测整个试验现象,分析了其滞回、承载力、刚度退化、耗能等抗震指标。结果结果表明:试件破坏过程明显经历了弹性段、塑性段、破坏段三个阶段,试件破坏模式主要为支撑受压失稳破坏,塑性变形主要累积在支撑体系上,整体呈现延性破坏特征;支撑断裂后,梁柱及T型钢节点无明显塑性变形,钢框架仍具有较高的安全储备,符合“强节点、弱构件”设计原则,表明了结构具有两道抗震防线;结论支撑与半刚接钢框架协同工作使得试件具有较高的抗侧刚度抵抗水平变形,且承载力较高、滞回性能稳定、耗能能力优良;单边螺栓在试验过程中的受力性能较普通高强螺栓并无较大差别,未出现严重的预紧力松弛现象,并能高效的保持螺栓预紧力。通过有限元数值模拟分析可知,减小支撑长细比,虽能有效提高结构的抗震性能,但长细比较小会导致支撑刚度增大,加速其余构件的损坏。故应以考虑结构的延性为前提,降低支撑的长细比,才能有效提高结构的抗震性能。

摘要：高性能混凝土(HPC)早期形变和变化规律的研究有助于指导高层建筑、大跨梁结构等的设计与施工。使用埋设型FBG应变传感器成功检测了HPC早期的变形特性,特别是混凝土硬化前后(浇注后24 h内)的变形情况。结果表明,硬化前后高性能混凝土的变形,特别是浇注初期24 h内变形增加很快,表现为温度膨胀变形和自收缩变形,影响其中长期性能。HPC构件配筋与否对温度变形没有影响,但由于受配筋骨架约束,自收缩相对无筋构件减小,总变形增大。不同尺寸构件的数据分析表明,HPC早期变形受构件尺寸影响很小。

摘要：在高性能混凝土构件无载荷养护早期,混凝土较大的自生收缩和温度变形在混凝土结构内部产生微裂纹将对高性能混凝土结构的耐久性产生不可忽视的影响。运用光纤布拉格光栅(FBG)埋设型传感器成功检测了高性能混凝土梁构件在其无载养护早期的应变和温度变化。由于布拉格光栅同时感应温度变化和应变,因此需要设置FBG温度传感器来补偿应变传感器的温度影响。FBG双传感器成功检测了高性能混凝土梁构件的早期变形性能和温度变化,试验结果表明高性能混凝土梁在养护早期无载阶段的自收缩变形比较大,浇注养护18 h达到430με的最大值,同时分析了减水剂用量对高性能混凝土早期变形性能的影响。

摘要：For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

摘要：The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.