摘要：A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was *** OTP memory is used for program and data *** is required to apply 5.5V to BL(bit-line)and 11V to WL(word-line)for a OTP cell of 0.35μm ETOX(EEPROM tunnel oxide)type by *** use 5V transistors on column data paths to reduce the area of column data paths since they require small *** addition,we secure device reliability by using HV(high-voltage)transistors in the WL ***,we change from a static logic to a dynamic logic used for the WL driver in the core ***,we optimize the WD(write data)switch ***,we can implement them with a small-area *** addition,we implement the address predecoder with a small-area logic *** area of the designed 32 kbit OTP with 5V and HV devices is 674.725μm×258.75μm(=0.1745mm2)and is 56.3% smaller than that using 3.3V devices.

摘要：For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.