摘要：Embedded systems used in real-time applications require low power, less area and high computation speed. For digital signal processing, image processing and communication applications, data are often received at a continuously high rate. The type of necessary arithmetic functions and matrix operations may vary greatly among different applications. The RTL-based design and verification of one or more of these functions could be time-consuming. Some High Level Synthesis tools reduce this design and verification time but may not be optimal or suitable for low power applications. The design tool proposed in this paper can improve the design time and reduce the verification process. The design tool offers a fast design and verification platform for important matrix operations. These operations range from simple addition to more complex matrix operations such as LU and QR factorizations. The proposed platform can improve design time by reducing verification cycle. This tool generates Verilog code and its testbench that can be realized in FPGA and VLSI systems. The designed system uses MATLAB-based verification and reporting.

摘要：This study presents the architecture and design flow of smart mobile sensing systems that performs wireless sensor data transmission, data analysis and display in real-time. Multiple wireless protocols are used for sensor data transmission including the Bluetooth, cellular data network and Wi-Fi for Internet access, and Near Field Communication (NFC). An Android smartphone is utilized to demonstrate the design concept of an Intelligent Personal Communication Node (iPCN) and to perform real-time sensor data acquisition, processing, analysis, display and transmission. Tested sensors include acceleration, temperature, electrocardiography (ECG) and phonocardiography (PCG). For computational capability tests, we have observed the signal processing performance of the smartphone by implementing fast Fourier transform (FFT) of the received ECG signal, and QRS detection algorithm for spontaneous heart beat rate (HBR) estimation. This system has also been tested for multiple sensor node communication and on-demand sensor data acquisition. The smart mobile sensing system can also be applied to any environment that requires real-time sensing and wireless remote monitoring.

摘要：In this paper, we present a new design flow for robust license plate localization and recognition. The algorithm consists of three stages: 1) license plate localization;2) character segmentation;and 3) feature extraction and character recognition. The algorithm uses Mexican hat operator for edge detection and Euler number of a binary image for identifying the license plate region. A pre-processing step using median filter and contrast enhancement is employed to improve the character segmentation performance in case of low resolution and blur images. A unique feature vector comprised of region properties, projection data and reflection symmetry coefficient has been proposed. Back propagation artificial neural network classifier has been used to train and test the neural network based on the extracted feature. A thorough testing of algorithm is performed on a database with varying test cases in terms of illumination and different plate conditions. Practical considerations like existence of another text block in an image, presence of dirt or shadow on or near license plate region, license plate with rows of characters and sensitivity to license plate dimensions have been addressed. The results are encouraging with success rate of 98.10% for license plate localization and 97.05% for character recognition.

摘要：This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis (HLS). HLS tools convert algorithms designed in C into hardware modules. This approach is a practical choice for developing complex applications. Nevertheless, certain hardware considerations are required when writing C applications for HLS tools. Hence, in order to demonstrate the fundamental hardware design concepts, a case studyis presented. Fast Fourier Transform (FFT) implementation in ANSI C is examined in order to explore the important design issues such as concurrency, data recurrences and memory accesses that need to be resolved before generating the hardware using HLS tools. There are additional language constraints that need to be addressed including use of pointers, recursion and floating point types.