摘要：In radio receivers,complete implementation of the software defined radio(SDR) concept is mainly limited by *** on bandpass sampling(BPS) theory,a flexible digital frontend(DFE) platform for SDR receiver is *** order to increase the processing speed,Gigabit Ethernet was applied in the platform at speed of 5×10~8 bit/*** appropriate design of interpolant according to the position of input RF signals,multi-band receiving can be realized in the platform with suppression more than 35 d B without changing hardware.

摘要：The problem of designing a digital frontend (DFE) was considered which can dynamically access or sense dual bands in any radio frequency (RF) regions without requiring hardware changes. In particular, second-order bandpass sampling (BPS) as a technique that enables to realize the multiband reception function was discussed. In a second-order BPS system, digital reconstruction filters were utilized to eliminate the interferences generated while down converting arbitrarily positioned RF-band signals by using the direct digitization method. However, the inaccuracy in the phase shift or the amplitude mismatch between the two sample streams may cause insufficient rejection of interference. Practical problems were studied, such as performance degradation in signal-to-interference ratio (SIR) and compensation methods to overcome them. In order to demonstrate the second- order BPS as a flexible DFE suitable for software-defined radio (SDR) or cognitive radio (CR), a DFE testbed with a reconfigurable structure was implemented. Moreover, with a view to further demonstrate the proposed compensation algorithms, experimental results show that dual bands are received simultaneously.

摘要：The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.