摘要：Reducin. the power an. en.rgy required by the device/circuit to operate is the main.aim of this paper. Here the n.w design.is implemen.ed to reduce the power con.umption.of the device usin. the triggerin. pulses. The proposed triggerin. method uses a complemen.ary MOS tran.istor (pMOS an. n.OS) as a voltage divider an. groun. leakage suppressor (i.e.);these design. are n.med as Trig01 an. Trig10 design.. In.Trig01 design.the pair of CMOS is placed in.the voltage divider part;similarly in.Trig10 design.the pair of CMOS is placed at the groun. leakage suppressor part. Stan.ard CMOS gates like n.T, n.n., n.R, EX-OR etc. are design.d with these techn.logies an. these gates are design.d with 180 n. techn.logy file in.the caden.e tool suite;compared to the n.rmal CMOS gates, the Bi-Trig gate con.ain. 4 in.uts an. 2 outputs. The two extra in.uts are used as Bi-Trig con.rol sign.lin. in.uts. There are 2 con.rol in.uts an. thus 22 = 4 combin.tion.of con.rollin. is don. (i.e.);both pMOS an. n.OS are On. both pMOS an. n.OS are OFF, pMOS On.an. n.OS OFF an. pMOS On.an. n.OS On. Depen.in. on.the usage of the circuit, the mode of operation.is switched to an. on. of the combin.tion. If the output of the circuit is n.t used an.where in.the total block, that specified circuit can.be switched in.o idle mode by mean. of switched OFF both the pMOS an. n.OS tran.istor in.the con.rol un.t. This reduces the leakage curren. an. also the power wastage of the circuits in.the total block. Bi-Trig con.rolled circuit reduces the power con.umption.an. leakage power of the circuit without affectin. a performan.e of the circuits.