摘要：We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.