摘要：A major concern in modern s.art-phones.and hand-held devices.is.a way of mitigating the time interval error (TIE) perceived at high-s.eed digital trans.ts.along the traces.of the circuit-board (rigid and or flexible) us.d in bas.band infras.ructures. Indicated here is.a way of adopting a planar fractal inductor configuration to improvis. the neces.ary time-delay in the trans.ts.of digital s.gnal phas. jitter and reduce the TIE. This.paper addres.es.s.s.ematic des.gn cons.derations.on fractal inductor geometry commens.rate with practical as.ects.of its.implementation as.delaylines.in the high-s.eed digital trans.orts.at the bas.band operations.of s.art-phone infras.ructures. Experimental res.lts.obtained from a tes. module are pres.nted to illus.rate the efficacy of the des.gn and acceptable delay performance of the tes. s.ructure commens.rate with the digital trans.orts.of interes..