摘要：This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.

摘要：The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.

摘要：This paper reports design of a CMOS optical receiver front-end using 0.18 μm technology. Design process is current associated with photodiode using trans-impedance amplifier (TIA) for wide bandwidth, high gain, low input referred noise and wide dynamic range. The Automated Gain Control (AGC) voltage is used to provide variable gain for multilevel signals. This design is simulated in 0.18 μm UMC technology for the performance analysis. The best simulation results are reported the maximum TIA gain of 67.26 dB? at 0 V AGC followed by a post amplifier gain of 86.70 dB?. The bandwidth range is 7.03 GHz to 11.5 GHz corresponding to 0 - 3 V AGC respectively. The input referred noise level value is 43.86 pA/√Hz up to 10 GHz frequency. In addition authors have obtained the common mode rejection ratio (CMRR) is 72.42 dB and rectified group delay is 144.48 ps. Verification of the design, reported results are compared with earlier published work and improvements obtained in the present results.